Silicon Labs introduces the PCI Express (PCIe) Gen1/2 2/3 fan-out buffer

     Silicon Labs announced the introduction of PCI Express (PCIe) Gen1/2 2/3 fan-out buffers, designed for data center applications including servers, storage, and switches. For today's leading x86 motherboards and server systems, the new Si5310x/11x/019 PCIe buffer is the industry's most energy-efficient fan-out buffer, effectively expanding Silicon Labs' growing PCIe timing product line. With flexible output quantity options, the new PCIe buffer fully meets 98% of x86-based server/memory board design requirements.

     For years, data center equipment manufacturers have had to choose from a limited number of vendors with PCIe Gen3 buffers certified by major x86 CPU and chipset vendors. These traditional PCIe buffers are typically based on power-hungry constant-current output technology that requires at least four off-chip terminal resistors and one reference resistor per output, increasing bill of Materials (BOM) costs. As energy and cooling costs become more critical to data center design, developers are increasingly looking for timing products that offer maximum energy efficiency while complying with the strict x86 motherboard specifications. Silicon Labs' Si5310x/11x/019 family of products provides device manufacturers with low-power, standards-compliant PCIe buffer products that are not only certified by major x86 CPU and chipset vendors, but also have strong technical support.

     More than 90% of existing motherboard designs still use PCIe buffers based on constant current output technology. To meet the needs of these existing markets, Silicon Labs' new Si53019 PCIe constant current buffer provides a fully certified direct replacement compatible solution with 30 percent less energy consumption compared to traditional solutions.

     To further reduce power consumption, Silicon Labs' Si5310x and Si5311x devices use an innovative push-pull output architecture that offers the industry's lowest power consumption PCIe buffer family. These devices consume 60% less power than constant current buffers, while reducing the number of off-chip resistors required per output, significantly reducing the number of off-chip devices and simplifying printed circuit board (PCB) design. For example, by using Silicon Labs' 19-way output Si53119 push-pull buffer instead of a traditional constant-current device, developers were able to save nearly 1W of energy consumption and eliminate 39 off-chip devices.

     Silicon Labs' Si5310x and Si5311x push-pull output chips are also the best PCIe timing solutions for systems designed for the new ARM® SoC-based hyperscale server and storage markets. Similar to x86-based designs, ARM-based SoC platforms for servers and storage devices use PCIe as the primary system data bus and interconnect mode. As system-level energy efficiency becomes the key to hyperscale architectures, the new Si5310x and Si5311x devices with push-pull outputs are ideal for server and storage platform designs, regardless of CPU architecture.

     In addition to considering energy consumption, manufacturers of data center equipment also face the challenge of maintaining signal integrity, as clock signals often need to be transmitted between boards up to 60 inches long. Over such a long distance, the rise and fall times of the PCIe clock will be longer and slower, which also leads to reduced jitter performance and higher packet loss rates in the system. Silicon Labs' PCIe Gen3 buffer is designed to be able to provide long distance clock signal transmission while maintaining compatibility with standard PCIe rise and fall time specifications, preventing increased jitter and increased packet loss rates.

     Silicon Labs' new family of PCIe buffers supports 6, 8, 12, 15, and 19 outputs with both constant current and push-pull output buffers, allowing developers to customize the best timing solution for each application. Silicon Labs' chips are pin-and function-compatible with traditional PCIe buffers, offering developers the best possible alternative with enhanced energy efficiency, signal integrity, and jitter performance.

     James Wilson, Director of Clock Product Marketing at Silicon Labs, said: "Mobile Internet traffic and cloud computing are driving faster, higher performance data center devices to choose high-precision timing solutions that support the PCIe standard and major x86 specifications. We have expanded our PCIe timing product line and now include PCIe Gen3 fan-out buffers that are fully x86-compliant, dramatically reducing the power, cost and complexity of data center equipment. "Our new PCIe product complements Silicon Labs' arbitrary frequency clock generators and provides a single-chip clock tree solution for server, switch and storage designs."

     Silicon Labs offers a broad clock product line, including frequency-flexible clock generators, jitter attenuators, clock buffers, PCIe clocks, and oscillators to meet a wide range of iot infrastructure applications. These high-performance timing solutions enable developers to provide a complete timing solution for data centers, core networks, wireless infrastructure, broadband access, and test and measurement design from a single one-stop shop.