Imagination announces the MIPS I6500-F, a CPU IP designed for safety-critical systems in the age of autonomous computing

Imagination Technologies has announced the launch of a highly scalable 64-bit MIPS multiprocessing solution that has been rigorously evaluated and validated to meet the functional safety (FuSa) requirements of ISO 26262 and IEC 61508 standards. For emerging safety-critical systems such as autonomous driving, industrial IoT and robotics, this solution is ideal for handling their compute-intensive tasks. The I6500-F goes beyond other FuSa CPU IP cores to provide a high-performance, efficient foundation to drive multicore designs for these systems, and can scale to 64 heterogeneous clusters in a single system, each consisting of multithreaded, multicore MIPS cpus and other accelerators.

FuSa is critical to all components in safety-critical systems, including the most critical CPU IP in SOCs. Applications such as autonomous driving and industrial control systems in smart factories require increasingly high processing power beyond what is currently provided by FuSa compliant CPU IP cores. As a result, customers can take advantage of the I6500-F's extended performance to effectively integrate increasing intelligence capabilities - including artificial intelligence technologies such as CNN and DNN - into their safety-critical equipment.

Jim Nicholas, executive vice President of MIPS Processor IP at Imagination, said: "We can provide the next generation of autonomous and intelligent systems with the performance they need to power their computation-intensive tasks. The I6500-F is a fully tested IP solution that ensures customers meet the most stringent security requirements. If you're developing SOCs for these types of systems today, the I6500-F is your best bet."

Drive advanced safety design

Building on the work of existing IP cores such as the MIPS P5600, Imagination is importing basic security technologies across its MIPS portfolio. The P5600 has been used in safety-critical designs to support highly reliable industrial environments.

It also continues Imagination's security technology collaboration with Mobileye. Mobileye's EyeQ®4 SoC for ADAS uses MIPS interAptiv and the M5150 CPU with software self-kernel testing, which is designed specifically for ASIL B. Its next generation EyeQ®5 SoC for autonomous vehicles is based on the I6500-F CPU and will be manufactured in a 7-nanometer FinFET process. EyeQ®5 is an open software platform on which customers can deploy their own algorithms - a capability enabled by MIPS architecture technology, including hardware virtualization. Mobileye SoC is now built into several ADAS systems.

Elchanan Rushinek, senior vice president of Engineering at Mobileye, said: "Our EyeQ®5 SoC will be the most advanced solution for fully autonomous vehicles expected in 2020. The ASIL B(D) feature in the I6500-F is key to ensuring that our chips achieve the highest level of security. The complete cache coherency between the CPU and the vision accelerator in the I6500-F makes it an ideal platform for heterogeneous computing and adds the unique capability of inter-thread communication to the real-time functionality. Our EyeQ SoCs of all generations deliver significant improvements in performance, efficiency and security, thanks to MIPS 'multithreaded cpus."

Target demanding automotive applications

Imagination has established methodologies and processes for design and safety and can provide documentation in accordance with ISO 26262 requirements, including safety planning, validation reviews and validation measures.

The I6500-F is designed to meet the requirements of the ASIL B(D) class, enabling the I6500-F to target automotive applications up to the stringent requirements of the ASIL D class. The IP was developed with the Safety Element out of Context (SEooC) security lifecycle in close collaboration with key partners, plus ResilTech S.r.l., an independent security evaluator. The design safety lifecycle of the I6500-F is closely aligned with the component supplier's security lifecycle and is based on ISO 26262, 2011 1st edition, but has taken into account best practices for IP in Part 11, which will be included in ISO 26262 2nd Edition. And has been published in the public DIS version.

ResilTech S.r.l. provides leading consulting services on functional safety, including independent technical safety analysis of hardware and software designs in safety-critical systems. Dr. Francesco Rossi, the company's Automotive Safety Solutions Manager, said: "When Imagination developed multiple FuSa IP cores, we worked closely with the MIPS team to ensure that its Safety Requirements Specification (SRS) met the stringent requirements of its early customers. Indeed, the results are very detailed and provide excellent value to SoC vendors."

The I6500-F is designed for FortifAI intelligent systems

The I6500-F is a new MIPS processor designed for the next generation of "FortifAI" intelligent systems - providing high system efficiency, scalable computing power, and increased levels of functional safety. Customers can ensure that MIPS FortifAI cpus deliver the high performance and security features required for compute-intensive tasks for a wide range of smart safety-critical applications.

Dominique Bonte, General Manager and Vice President of ABI Research, said: "With the introduction of the MIPS I6500-F, Imagination has brought functional security (FuSa) to the high-performance CPU computing required for IoT systems and vehicles. Thanks to its SEooC development process designed for FuSa - its certification process supports its multi-threaded, multi-core heterogeneous architecture - the I6500-F will help accelerate time-to-market for AI-based ASIL-D SoC designs for autonomous vehicles. This will meet the needs of the automotive supply ecosystem as it moves aggressively towards L4/5 autonomous technology."

Based on the popular MIPS I6500 CPU, the MIPS I6500-F is a 64-bit, multi-threaded, multi-core, multi-cluster CPU with scalability from embedded systems to the cloud. Both IP cores can consistently build optimized CPU core configurations within a single cluster (" internal heterogeneity "), as well as various CPU cluster configurations and GPU or accelerator clusters on the chip (" external heterogeneity "). With unique features such as simultaneous multithreading (SMT) and hardware virtualization (VZ), this IP offers several benefits, including "zero context switching" for applications to respond instantly. It also supports OmniShield technology, which provides a strong foundation for security-by-separation.

A QMS development process that addresses systemic failures is the foundation of the MIPS I6500-F. Support for run-time LBIST, as well as critical registers and embedded memory throughout the kernel, are fully redundant, allowing it to correctly detect both temporary and permanent failures. The redundancy function is extended in the Coherence Manager (CM3) and IO Consistency Unit (IOCU) to fully protect all multi-core clusters of the MIPS I6500-F.

Technical document

The I6500-F provides complete safety work product content, including safety cases such as the independent FMEDA Safety analysis report written by ResilTech to assist customers in meeting ISO 26262 safety compliance. Imagination will also provide security consulting support services to assist customers with SoC level integration and security analysis preparation to achieve ISO 26262 compliance.